Twin NAND device structure, array operations and fabrication method

ABSTRACT

A method for making a twin MONOS memory array is described where two nitride storage sites lay under the memory cell word gate. The fabrication techniques incorporate self alignment techniques to produce a small cell in which N+ diffusion the nitride storage sites are defined by sidewalls. The memory cell is used in an NAND array where the memory operations are controlled by voltages on the word lines and column selectors. Each storage site within the memory cell is separately programmed and read by application of voltages to the selected cell through the selected word line whereas the unselected word lines are used to pass drain and source voltages to the selected cell from upper and lower column voltages.

[0001] This application claims priority to Provisional PatentApplication serial No. 60/311,879, filed on Aug. 13, 2001, which isherein incorporated by reference

BACKGROUND OF THE INVENTION

[0002] 1. Field of Invention

[0003] The present invention is related to semiconductor memory and moreparticular non-volatile NAND memory arrays.

[0004] 2. Description of Related Art

[0005] In F. Masuoka et al., “A New NAND Cell for Ultra High Density5V-only EEPROMs”, May 1988, Proc 1988 Symposium on VLSI Technology, IV-5pp33-34) a floating gate NAND cell, shown in FIG. 1A of prior art, isdescribed that has been used widely as Non-volatile memory. Since thememory cell is placed in series without any contact, the density is veryhigh even though the process complexity is high and the read currentlevel is very small. The storage element in the flash NAND is apolysilicon floating gate 200 residing under a word line 201 in theexample shown in FIG. 1A. The floating gate can be replaced by a nitridelayer sandwiched between bottom and top oxide layers(Oxide-Nitride-Oxide) 202 laying under a word gate 201 as shown in theexample in FIG. 1B and FIG. 1C of prior art. The ONO layer sandwichstores electron or hole charges in the nitride or interface trap sitesas suggested in Y. Hayashi et al. “Nonvolatile Semiconductor memory andits Programming Method”, JP 11-22940, Dec. 5, 1997. This ONO storageapproach for the MONOS NAND simplifies the process significantlycompared to the floating gate approach. The floating gate NAND utilizesmulti-level storage and provides density factor at least 2 times,whereas a the twin MONOS device of the present invention improvesdensity by storing charges on both device edges in a single planar FETdevices. In U.S. Pat. No. 5,768,192 (Eitan) a non-volatile semiconductormemory cell utilizing asymmetrical charge trapping is disclosed.However, the memory cell device suffers from a threshold shift aftermany program and erase cycles because the electron mean free path islarger than hole mean free path. In U.S. Pat. No. 4,943,943 (Hayashi etal.) a read-out circuit for a semiconductor nonvolatile memory isdescribed which is capable of extracting a widely fluctuating outputvoltage using a reverse read.

[0006] In the present invention, the nitride storage element under theword gate is very small and well defined so that the hole injection forprogram is applicable over the whole nitride storage region. Erase isachieved by FN electron injection, and once the nitride region islimited and optimized, then the voltage required for hole injection canbe almost halved. By introducing a trap free oxide region between thetwo nitride storage sites, the threshold instability from program anderase cycles due to the miss match of hole and electron mean free pathsis solved assuring high endurance. The voltage reduction in FN injectionis achieved by reducing nitride thickness down to few atomic layers.Thus a low voltage and high density operation is achieved for the MONOSNAND structure of the present invention.

SUMMARY OF THE INVENTION

[0007] It is an objective of the present invention to provide a twinMONOS memory cell where the two storage sites are beneath a word gate.

[0008] It is another objective of the present invention to couple cellsin a column together with diffusions located between memory cells.

[0009] It is still another objective to isolate cells between columnswith a shallow trench isolation.

[0010] It is also another objective of the present invention to use thetwin MONOS memory cell with two storage sites beneath the word gate in aNAND memory array.

[0011] It is yet an objective of the present invention to erase andprogram the storage sites using electron injection with FN tunneling andhot hole injection with band to band tunneling, respectively.

[0012] It is also yet an objective of the present invention tosequentially read odd (or even) storage sites on a column.

[0013] It is still yet an objective of the present invention to erase byblock, program and read by storage cell.

[0014] A twin MONOS NAND memory array is produced where the memory cellcontains two storage sites located below a word gate. Exclusive ofcolumn select, column voltages and word line voltages, no other controlsare required to control memory operations. Unselected word lines areused to pass upper and lower column voltages to source and drain of theselected cell. The voltages on the source and drain of each cell alongwith the word gate voltage control the memory operations of each cell.

[0015] The twin MONOS memory cells are constructed on a P-type well byestablishing blocks of SiO₂ under which N-type regions were previouslyimplanted. The N-type region comprises a lightly doped area within whichis a heavily doped area. Silicon nitride deposited on the walls of theblocks and the area between blocks is masked by disposable sidewalls andetched to leave an “L” shaped element on adjacent sides of the blocks.The foot of the “L” silicon nitride shape that extends part way into thearea between the SiO₂ blocks is used as the storage sites for the twinMONOS memory cell. The SiN can be another insulator material differentfrom the bottom and top insulator such as Ta₂O₅ and Zr O₂ etc. Theobjective is to create trap sites for electron and hole storage atdifferent insulator interfaces. A polysilicon layer is deposited in theregion between blocks and over the “L” shaped silicon nitride. Thepolysilicon layer forms a word gate for the memory cell and iscontinuous over the width of the memory array becoming a word line. Thediffusion areas under the SiO₂ connect memory cells in a columntogether, providing a drain for one cell and a source for the adjacentcell.

[0016] Alternative fabrication method after defining the SiO₂ block isalso provided. ONO(Oxide-Nitride-Oxide) and polysilicon are subsequentlydeposited on the walls of the blocks. The area between blocks is maskedby sidewall polysilicon and etched to leave an “L” shaped ONO element onadjacent sides of the blocks. The foot of the “L” shaped ONO thatextends part way into the area between the SiO₂ blocks is used as thestorage sites for the twin MONOS memory cell. A gate oxide is grown onthe exposed substrate between the L shapes. The oxide is also grown onthe polysilicon sidewalls. A polysilicon layer is deposited in a trenchbetween the polysilicon sidewalls and recessed to expose and remove theoxide on the polysilicon sidewalls. The polysilicon sidewall gatesfacing each other are connected by a tungsten stud process, which formsa word gate for the memory cell.

[0017] At the top and bottom of each column are upper and lower selectorgates that select even or odd columns with voltages required to open orclose the gates. With an upper and lower column voltage selected by theupper and lower selector gates, the unselected word lines bias theunselected memory cells to pass the upper and lower column voltages tothe drain and source of the selected memory cell. Thus the combinationof the voltage on the selected word line and the upper and lower columnvoltages passed by the unselected word lines, the selected storage sitewithin a memory cell is read and programmed, and both storage sites of ablock of memory cells are erased.

[0018] The memory density is doubled as compared to conventionalfloating gate devices because there are two storage elements under asingle word gate. A shorter and thinner high voltage device is produced,which solves scaling and performance issues. Program and erase voltagereduction is possible as a result of not having to consider couplingratios. Process simplicity is a result of to eliminating floating gateelements and by the method used to produce the twin storage sites. Thenitride under the word gate can be continuous, but extra electrons aretrapped at the middle of the channel if holes do not reach the center ofthe channel due to the short mean free path. This causes the centerthreshold to gradually get high after many program and erase cycles.This threshold instability due to uncontrolled electron charge at themiddle of the channel is eliminated by separating the nitride layer atthe middle and by providing charge trap free oxide in the middle of thechannel. The controlled short storage elements allow a large thresholdvoltage fall off in forward read operations, and the large Vt fall offmay extend the use of multi-level storage in the reverse read mode.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] This invention will be described with reference to theaccompanying drawings, wherein:

[0020]FIG. 1A shows a diagram of a portion of a floating gate NANDmemory array of prior art,

[0021]FIG. 1B shows a diagram of a portion of a floating gate NANDmemory array where the floating gate area is constructed using an ONOregion under the control gate.

[0022]FIG. 2 shows a schematic diagram of a twin MONOS NAND memory arrayof the present invention,

[0023]FIG. 3A and 3B show diagrams of the memory array structure of thepresent invention.

[0024]FIG. 4A shows a diagram for an erase operation of a memory cell ofthe present invention, where device 31 and 32 are both charged withelectrons by FN tunnel injection,

[0025]FIG. 4B shows a diagram for a program operation of a memory cellof the present invention, where a device is programmed by hot holeinjection generated by band to band tunneling,

[0026]FIG. 5A shows a schematic diagram for a program operation of aselected cell in the memory array of the present invention,

[0027]FIG. 5B shows a schematic diagram for an erase operation of ablock of cells in the memory array of the present invention,

[0028]FIG. 6A shows a diagram of three device components in a singlememory cell of the present invention,

[0029]FIG. 6B shows a table of possible threshold conditions in thethree devices in a single memory cell including the net threshold of thecombined memory cell.

[0030]FIG. 6C shows the threshold behavior of a memory cell fordifferent memory storage states provided in FIG. 6B.

[0031]FIG. 7 shows a schematic diagram for a read operation of aselected cell in the memory array of the present invention, and

[0032]FIG. 8A through 8I show process steps to produce the twin MONOSmemory cell of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0033] In FIG. 2 is shown two columns of an NAND array using the twinMONOS memory cells of the present invention. At the top of each columnare selector gates 10 that connect an upper column voltage Vu to acolumn of memory cells. At the bottom of each column are selector gates11 that connect a bottom voltage Vb to a column of memory cells. Aselector voltage S0 selects the selector gates for a first column andselector S1 selects the voltages for a second memory column. Each memorycell 12 is constructed with two storage sites 13 and 14 under a wordgate 15. The word gates of a row of memory cells are connected togetherwith a word line 16. Memory cells in a column are connected together byan N-type diffusion in a P-type substrate. The array can also be made onan N-type substrate where the diffusions connecting together cells in acolumn would be a P-type substrate or a P-Well.

[0034]FIG. 3A shows a cross sectional diagram of a portion of a columnof memory cells of the present invention. The “L” shaped nitrideelements 20 lay between the polysilicon word lines and the oxideinsulator blocks 22. The feet of the “L” shaped nitride lay under theword gate 21 and provide storage sites for the twin MONOS memory cellswhere the nitride layer can be replaced by other insulators having lowerenergy gap than that for silicon dioxide. Below each oxide block 22 layan N-type diffusion 23. The diffusion 23 and the adjacent diffusion 24provide a source and a drain for a memory cell constructed of the two“L” shaped nitride elements 20 and the word gate that is a part of theword line 21. FIG. 3B shows shallow trench isolation 28 that liesbetween columns to separate the cells in adjacent columns.

[0035] Continuing to refer to FIG. 3A, under each word gate 21 and atedges of the diffusions 23 and 24, a short and thin nitride foot of the“L” shaped element 20 is placed to provide charge storage havingapproximately about 20-40 nm in length and thickness ranging from a fewatomic layers to 15 nm. The middle of the word gate 21 does not have anunderlying nitride region and the gate oxide thickness under thepolysilicon word gate 21 is approximately about 8-12 nm. The oxide underthe nitride foot region 20 is approximately about 2.5-5 nm, and thenitride foot thickness is approximately about 2.5-5 nm. The top oxideover the nitride layer 20 is needed to block electrons injected by FNtunneling from the bottom silicon; therefore, the top oxide should beslightly thicker than the bottom oxide.

[0036] In FIG. 4A is shown a diagram demonstrating an erase operation.In an erase operation electrons are injected 30 into the nitride layers31 and 32 by FN tunneling with a positive voltage approximately about10V on the word gate 21 and 0V on the diffusions 23 and 24 and thesubstrate 33. The 10V between the word gate 21, and silicon substrate 33and diffusions 23 and 24 can be proportioned such that 6V is on the wordgate and 4V on the silicon substrate. Both storage nitride elements 31and 32 under each word gate are injected and filled with electronssimultaneously.

[0037] In FIG. 4B is shown a diagram demonstrating a program operation.A program operation is defined as an electron ejection 35 or holeinjection with a negative bias of approximately about (−2 to −5V) on theselected word gate 21 and positive bias of approximately about (4 to 5V)on the diffusion 23 under the selected storage site 31. Under this biascondition, the slightly inside of N-junction 23 is depleted by thenegative word gate voltage and holes 35 are generated by band to bandtunneling. The holes are accelerated by the potential between the drainvoltage and the substrate, and injected into the storage node 31 in FIG.4B.through the bottom oxide if the hole energy is higher than the oxidebarrier height. The diffusion 24 under the unselected storage site 32 isbiased to ground. Since the negative gate bias provides an off state inthe N-channel device, one diffusion 23 in the transistor can be a highvoltage and the other diffusion 24 can be ground without channelcurrent. Thus stored electrons in only one of the storage sites 31 and32 under each word gate can be ejected by selecting a positive voltageon diffusion 23 without affecting the other storage site with holeinjection. It should be noted that the voltage conditions among thenodes in FIG. 4A and 4B are relative to one another.

[0038] In FIG. 5A is shown a schematic diagram demonstrating aprogramming operation on a selected storage site 40, which is circled.In this demonstration, the selected storage site to be programmed andeject electrons is the upper storage site 40 and the unselected storagesite is the lower storage site 41. Both the upper and lower storagesites reside under the selected word gate 42 where the word gate isbiased to approximately about a negative 4 volts. The drain of selecttransistor 43 is biased to approximately about a positive 4V. The selecttransistor drain bias of 4 Volts is passed to the diffusion 47 under theselected storage site 40 by applying sufficient voltage of approximatelyabout 6V on the gate of the upper select transistor 43 and theunselected word gates 44. A ground potential is applied to the source ofthe bottom select transistor 45, which is connected to the diffusion 48under the unselected storage site 41 when gate of the bottom selecttransistor and the unselected word gates 46 are biased to a few voltsabove ground (arbitrarily chosen to be 4 volts for this demonstration).The application of the higher voltage on the upper unselected word gates44 is slowly ramped in order to minimize electron injection into thenitride under an unselected word gate, which may occur when thediffusion nodes are at an initial 0V.

[0039] In FIG. 5b is shown a schematic diagram demonstrating an eraseoperation on a portion of a block of memory cells. The upper and lowerselected transistors are selected with a select voltage of 3V allowingthe ground potential on the bit lines to be passed to the memory cellsin the column. A high voltage (+10V) is applied to the word gates 49 ofeach memory cell. In the erase operation electrons are injected into thenitride layers, typified by 40 and 41, by FN tunneling with the positiveword gate voltage of approximately about 10V and 0V on the diffusions 47and 48 and the substrate. Both storage nitride elements 40 and 41 undereach word gate are injected and filled with electrons simultaneously.

[0040] Referring to FIG. 6A, a twin MONOS memory cell of the presentinvention is shown with a word gate 70, two nitride storage sites 71 and72, a drain 73 and a source 74. Three voltage regions (a), (b) and (c)are shown which traverse the channel under the word gate. A voltage VDSis applied to the drain 73 with the source connected to ground. Whensome electrons have been stored in the drain side nitride storage site71, the Vt of region (a) is increased to 1.5V from 0.5V. When a voltageof about 1V is applied to the drain, the Vt towards the drain 73 isreduced to a Vt of approximately 0.5V from 1.5V since the depletionregion extends beyond the short (approximately 20-30 nm) nitride region71, while the Vt of the source side 72 is unaffected and controls thechannel current.

[0041] In FIG. 6B is shown values for Vt in regions (a), (b) and (c).For condition (i), all of the Vt in the region (a), (b) and (c) are0.5V, then the net Vt of the three combined devices in series is 0.5V.For condition (ii), where there is a charge on the drain side storagesite on 71, there is about 1.5V at low drain voltage. However, as thedrain voltage increases, the net threshold voltage decreases quicklyfrom 1.5V to 0.5V as shown in FIG. 6C due to the drain depletionextension beyond the nitride layer. For condition (iii) and (iv), whenthere is stored charge on the source side storage 72 in FIG. 6A, thedrain voltage does not easily affect the source device and the net Vt ofthe memory cell determined by the source side Vt of 1.5V. This meansthat when small voltage, as 1.5V, is applied to the drain, the memorystate in short channel device 71 at the drain can be ignored and thememory state of the source side device 72 can be correctly read even ifthe channel is extremely short.

[0042] Referring to FIG. 7, a schematic diagram of the present inventionis shown demonstrating a read operation. When the selected storage site53 is read, the selected word gate 54 is biased to about 1.5V near theprogrammed threshold voltage. The bottom diffusion 50 used as the drainis biased to approximately about 1.2V and the top diffusion 51 is biasedto ground. The Vt of the bottom storage site 55 is reduced below 0.5V bythe voltage (1.2V) of the drain 50 even when electrons are stored in thenitride storage site 55. If the top nitride storage site 53 is chargedwith electrons making the Vt near the upper diffusion 51 approximately1.5V, there is no current flow. If the upper storage site 53 is notcharged and has a low Vt, channel current will flow. Thus, the state ofcharge on the upper storage site 53 is determined by measuring thecolumn current.

[0043] Continuing to refer to FIG. 7, the 1.2V connected to the bottomdiffusion 50 is obtained by biasing the source of the bottom selecttransistor 56 to approximately 1.2V. The unselected word gates 57 arebiased to approximately 3V to pass the 1.2V to the bottom diffusion 50.The source of top select transistor 58 is biased to ground and theunselected word gates 59 are biased to approximately 3V to pass theground potential to the upper diffusion 51. When the bottom storage site55 is read, the voltages connected to the select transistors 56 and 58are reversed so that 1.2V is applied to the top select transistor 58 andground is applied to the bottom select transistor 56. The drain voltageof approximately 1.2 V is then applied to the top diffusion 51 throughthe top select transistor 58, and the bottom diffusion 50 is biased toground through the bottom select transistor 56.

[0044]FIG. 8A, through 8F show a fabrication method for an N channelTwin MONOS memory array. In FIG. 8A a P-type silicon substrate 90 isdoped with the surface concentration in the range of approximately about5E17 to 1.5E18 atoms per cm². Shallow trench isolation (not shown) isformed in areas between columns of memory cells. Then a gate oxide 91 inthe range of approximately about 2 nm to 5 nm is grown. A polysiliconlayer 92 in the range of approximately between of 150 nm to 250 nm isCVD (chemical vacuum deposited) followed by a nitride deposition 93 inthe range of approximately about 100 nm to 150 nm. The photo resist 94is patterned to define areas for an N+ deposition using conventionalphotolithography.

[0045] Referring to FIG. 8B, the nitride and the polysilicon are etchedusing the photo resist 94 as a mask. Then As (arsenic) is implanted at aconcentration of approximately between 3E12 and 3E13 atoms per cm³ at anenergy level of approximately between 15 keV and 20 keV to create alightly doped region 94. After the lightly doped regions are implanted,an oxide layer of in the range of approximately about 30 nm to 60 nm isdeposited by CVD and etched vertically leaving sidewall spacers 95having a thickness of approximately between 25 nm to 55 nm, whichsuppresses the out diffusion of N+ under the nitride storage region. Aheavily doped N+ region 96 is implanted with As to a concentration ofapproximately about 1.5E15 atom per cm² at an energy level betweenapproximately 15 keV and 25 keV.

[0046] In FIG. 8C a CVD oxide 98 in thickness in the range ofapproximately between 250 nm and 400 nm is deposited, and then the oxide98 is chemically mechanically polished (CMP) stopping at nitride 93. Theoxide isolation layer 98 is self-aligned to the diffusions 94 and 96.

[0047] Referring to FIG. 8D, the nitride layer 93 is selectivelyremoved, and the, polysilicon 92 is also carefully and selectivelyetched out by a chemical dry etch. The remaining oxide 91 of a thicknessof approximately 3.0 nm is etched out. Then a fresh gate oxide 100having a thickness of approximately between 2.5 nm and 5 nm is thermallygrown followed by nitride deposition 100 to a thickness of approximatelybetween 3 nm and 9 nm. A disposable sidewall spacer (DWS) 102 isdeposited to a thickness of approximately between 25 nm and 40 nm usinga material such as polysilicon, BPSG (borophosphosilicate glass) oroxynitride, which can be selectively etched against the silicon oxideisolation layer 98. After the spacer 102 is etched, exposed areas of thenitride layer 101 are etched out using the DSW as the mask.

[0048] Referring to FIG. 8E, after the DSW 102 is selectively removed,the remained nitride layer 101 and bottom silicon 100 are oxidized 103by ISSG (InSitu Steam Generation) tool and an additional thermaloxidation is used to grow approximately between 5 nm and 6 nm on thenitride 101. A thickness of approximately between 3 nm and 4 nm of thenitride 101 is converted to a thickness of approximately between 5 nmand 6 nm of oxide. The remaining nitride thickness after ISSG oxidationis a range approximately between few atomic layers and 6 nm. The oxideis also grown on the exposed substrate silicon regions in between theL-shaped nitride pair to approximately between 8 nm and 12 nm.

[0049] Referring to FIG. 8F, a word gate polysilicon 105 ofapproximately about 250 nm is deposited by CVD and the polysilicon 105is polished by CMP forming the polysilicon word gate between SiO₂ studs98 over N+region. The polygate 105 can be silicided with Cobalt orTitanium.

[0050]FIG. 8G through 8I show an alternative fabrication method for an Nchannel Twin MONOS memory array, following FIG. 8C. Referring to FIG.8G, after the peripheral area is protected by oxide mask (not shown),the nitride layer 93 in memory area is selectively removed, and thepolysilicon 92 is also carefully and selectively etched out by achemical dry etch, the remaining oxide 91 of a thickness ofapproximately 3.0 nm is etched out. Then a fresh gate oxide 100 having athickness of approximately between 2.5 nm and 5 nm is thermally grownfollowed by nitride deposition 106 to a thickness of approximatelybetween few atomic layer and 9 nm. A subsequent top oxide 107 is formedto a thickness of approximately between 4 nm and 7 nm. The top oxideformation 107 can be either CVD (chemical vapor deposition) such as HTOor thermal growth with ISSG, for example. The nitride depositionthickness for thermal top oxide is carefully defined since the nitrideis estimated to lose about two thirds of its thickness to the top oxideduring the thermal oxidation. After oxidation the remaining nitridethickness is approximately between few atomic layers to 6 nm. Theoperation voltages can be reduced if the nitride is a few atomic layers.The ultra thin nitride is also applicable for any other MONOS devices.The polysilicon 108 is deposited to a thickness of approximately between25 nm and 40 nm and vertically etched to the top oxide 107. After thepolysilicon 108 is etched, the top oxide layer 107, the nitride layer106 and the bottom oxide layer 100 in the exposed area are successivelyetched out using the polysilicon sidewalls 108 as the mask. This forms avoid 112 between the sidewalls, which go to the surface of the substrate90.

[0051] Referring to FIG. 8H, thermal oxide 109 having a thickness ofapproximately between 2.5 and 6 nm on substrate silicon is grown overexposed substrate 90, the exposed edges of the oxide 100 and 107, theexposed edge of the nitride 106 and the polysilicon sidewall 108.Another layer of polysilicon 110 is deposited to into the void 112 andthen the poly silicon 110 is vertically etched to the half way height ofthe word gate to expose the oxide 109 on polysilicon 108. This isfollowed by an oxide etch to expose the polysilicon and the nitride inthe logic area (not shown). Then nitride in logic area is selectivelyremoved.

[0052] Referring to FIG. 8I, a barrier metal such as titanium nitrideand tungsten 111 is deposited to connect side wall polysilicon 108 andpolysilicon 110 into a word gate and to connect to agate polysilicon inthe peripheral area (not shown), followed by CMP (chemical mechanicalpolish) to remove unnecessary tungsten. The process sequence can beshared with a contact stud process.

[0053] While the invention has been particularly shown and describedwith reference to preferred embodiments thereof, it will be understoodby those skilled in the art that various changes in form and details maybe made without departing from the spirit and scope of the invention.

What is claimed is:
 1. A method to produce a twin MONOS memory cellarray, comprising: a) preparing a semiconductor substrate to form cellsof a twin MONOS memory array, b) forming mask elements on a surface ofsaid semiconductor substrate, c) implanting a lightly doped regionbetween said mask elements and within said lightly doped regionimplanting a heavily doped region, d) forming a first insulator betweensaid mask elements over said lightly doped region, e) planarizing thesurface of said substrate, and stopping when said mask elements aredetected, f) removing said mask elements and forming a second insulatorover the surface of said substrate, g) forming sidewall spacers onvertical edges of said second insulator between regions of said firstinsulator and removing exposed areas of said second insulator, h)removing said sidewall spacers and forming a third insulator oversurface of said substrate, i) forming a conductive layer on said thirdinsulator between said regions of the first insulator.
 2. The method ofclaim 1, wherein preparing said semiconductor substrate furthercomprising: a) forming shallow trench isolation in locations betweencolumns of cells of said memory array, b) growing a gate oxide ofbetween about 2-5 nm.
 3. The method of claim 1 wherein saidsemiconductor substrate is a p-type substrate with a surfaceconcentration of between about 5E17 and 1.5E18 atoms per cm³.
 4. Themethod of claim 1, wherein forming said mask elements further comprises:a) depositing between about 100-250 nm of polysilicon using CVD, b)depositing on said polysilicon a nitride to a thickness between about100-150 nm, c) patterning and etching said mask elements.
 5. The methodof claim 1, wherein implanting said lightly doped region is to aconcentration of between about 3E12 and 3E13 atoms per cm³.
 6. Themethod of claim 5, wherein implanting said lightly doped region is at anenergy level of between about 15-20 keV.
 7. The method of claim 1,wherein implanting said heavily doped region further comprises: a)forming said sidewall spacers on said mask elements partially extendingover said lightly doped region, b) implanting said heavily doped regionto a concentration of approximately about 1.5E15 atoms per cm³.
 8. Themethod of claim 7, wherein implanting said heavily doped region is at anenergy level of 15-25 keV.
 9. The method of claim 1, wherein formingsaid first insulator between said mask elements is done by depositing anoxide using CVD to a thickness of between about 250-400 nm.
 10. Themethod of claim 1, wherein planarizing said surface of the substrateuses a chemical and mechanical polish stopping at a nitride layer ofsaid mask elements.
 11. The method of claim 1, wherein removing saidmask elements further comprises: a) removing an upper nitride layerusing a selective etch, b) removing a polysilicon layer using aselective etch using a dry chemical etch, c) removing a gate isolationoxide formed during said preparation of said substrate, d) growing a newgate oxide using a thermal process to a thickness of 2.5-5 nm.
 12. Themethod of claim 1, wherein forming a second insulator is done bydepositing a nitride at a thickness of between about 6-9 nm.
 13. Themethod of claim 1, wherein forming said sidewall spacers is done with adisposable material which can be selectively etched against said firstinsulator comprising silicon oxide.
 14. The method of claim 1 whereinforming said third insulator by ISSG (InSitu Steam Generation) furthercomprising: a) growing an oxide on said second insulator to a thicknessof approximately between 5-6 nm, b) growing said oxide on surface ofsubstrate to a thickness of approximately between 8-12 nm on saidsubstrate where exposed areas of said second insulator were removed. 15.The method of claim 1, wherein forming a conductive layer furthercomprises: a) depositing polysilicon by CVD to a thickness ofapproximately about 250 nm, b) polishing said polysilicon to planarizesurface of said substrate using chemical mechanical polishing, c)siliciding said polysilicon with Co or Ti.
 16. A method to create cellsfor a twin MONOS memory array, comprising: a) a means for depositing anarray of N-type regions into a semiconductor substrate to definelocations of cells for a twin MONOS memory, b) a means for creating afirst insulator over said N-type region in a defined shape, c) a meansfor covering sidewalls of said first insulator with a thin layer of asecond insulator wherein said second insulator extends partially into aspace between two adjacent first insulators at a surface of saidsubstrate forming an “L” like shape, d) a means for forming a thin layerof a third insulator over said second insulator in said space, e) ameans for filling said space with a conductive layer covering saidsecond and third insulators.
 17. The method of claim 16, wherein saidN-type region comprises a lightly doped region within which is a heavilydoped region.
 18. The method of claim 16, wherein said defined shape ofsaid first insulator is created by CVD of an oxide between formed maskelements on the surface of said substrate and by removing said maskelements.
 19. The method of claim 16, wherein said “L” like shape ofsaid second insulator is formed by depositing a nitride on said firstinsulator, protecting said nitride with sidewalls covering said nitrideon sides of said first insulator and etching exposed areas of saidnitride.
 20. The method of claim 19, wherein two adjacent feet of said“L” like shape of said nitride within said space forms two storage sitesof said memory cell.
 21. The method of claim 16, wherein said conductivelayer is formed by a CVD of a polysilicon into said space betweenadjacent first insulators to create a word gate for said memory cell.22. The method of claim 21, wherein said conductive layer extends acrossa row of said cells to form a word line for said memory.
 23. The methodof claim 17, wherein said N-type region connects between adjacent cellsin a column.
 23. A twin MONOS NAND memory array, comprising: a) an arrayof twin MONOS memory cells arranged in rows and columns and forming aNAND memory array, b) a word gate located over two storage sites of eachmemory cell of said memory cells, c) a diffusion forming a source and adrain connecting between said memory cells in a column d) a firstselector gate located at top of a column and connected to a first memorycell in said column. e) a second selector gate located at a bottom of acolumn and connected to a last memory cell in said column
 24. The memoryarray of claim 23, wherein said word gate is a part of a word line,which is further a row of said word gates.
 25. The memory array of claim23, wherein said source and said drain are formed by a single diffusionlocated between adjacent memory cells in said column.
 26. The memoryarray of claim 23, wherein said storage sites are nitride elementslocated below said word gate.
 27. The memory array of claim 23, whereinsaid first and second selector gates select said column of memory cellsto allow memory operations to be performed.
 28. The memory array ofclaim 23, wherein said diffusions in rows are isolated from each otherby a shallow trench isolation.
 29. A NAND memory array using twin MONOSmemory cells, comprising: a) a means to locate two storage sites undereach word gate of a twin MONOS memory array, b) a means for connectingtogether said word gates in a row of said memory array, c) a means forconnecting together a plurality of memory cells in a column of saidmemory array, wherein said column has an upper voltage and lowervoltage, d) a means for selecting said upper voltage to be connected tosaid column, e) a means for selecting said lower voltage to be connectedto said column, f) a means for performing memory operations by selectingsaid upper and lower voltages and by applying a plurality of voltages tothe word gates of said plurality of cells in said column.
 30. The memoryarray of claim 29, wherein said storage sites are nitride structuresextending beneath said word gates.
 31. The memory array of claim 29,wherein said means for connecting word gates together in a row is a wordline deposited across said memory array and forming the word gates ofeach memory cell in said row.
 32. The memory array of claim 29, whereinsaid means for connecting together said plurality of memory cells in acolumn is through a diffusion formed between each memory cell of saidplurality of cells in said column.
 33. A method for block erase ofstorage sites of a twin MONOS NAND memory array, comprising: a) applyinga high positive voltage to a selected word line, b) applying a lowvoltage to unselected word lines, c) applying a ground potential to adrain of an upper column selector gate, e) applying a ground potentialto a source of a lower column selector, f) selecting said upper andlower column selectors and erasing both storage sites of each cell in ablock of cells.
 34. The method for block erase of claim 34, wherein saidlow voltage is of sufficient magnitude to allow the ground potential tobe connected to a source and a drain of each cell in said block of cellsthrough unselected cell in each column containing said block.
 35. Themethod for block erase of claim 34, wherein erasing storage sites is anoperation whereby electrons are injected into said storage sites by FNtunneling.
 36. A method of programming storage sites in a twin MONOSNAND array, comprising: a) selecting a first storage site to beprogrammed of two storage sites contained within a selected memory cellof a column memory cells, b) connecting a negative voltage to a wordgate of said selected memory cell, c) connecting a positive voltage to afirst diffusion extending under said first storage site, d) connecting aground potential to a second diffusion extending under a second storagesite of said two storage sites, e) programming said first storage site.37. The method of programming of claim 37, wherein programming saidfirst storage site is an operation whereby electrons are ejected fromsaid first storage site by FN tunneling or hole injection.
 38. Themethod of programming of claim 37, wherein connecting said positivevoltage to said first diffusion further comprises: a) connecting saidpositive voltage from a column selector gate by selecting said selectorgate, b) connecting a word line voltage higher in value than saidpositive voltage to unselected word gates in said column between saidcolumn selector gate and said first diffusion.
 39. The method ofprogramming of claim 37, wherein connecting said ground potential tosaid second diffusion further comprises: a) connecting said groundpotential from a column selector gate by selecting said selector gate,b) connecting a word line voltage higher in value than said groundpotential to unselected word gates in said column between said columnselector gate and said second diffusion.
 40. A method of reading storagesites in a twin MONOS NAND array, comprising: a) selecting a firststorage site to be read from two storage sites contained within aselected memory cell of a column memory cells, b) connecting a firstpositive voltage to a word gate of said selected memory cell, c)connecting a ground potential to a first diffusion extending under saidfirst storage site to be read, c) connecting a second positive voltageto a second diffusion extending under a second storage site not beingread, e) reading a current when the word gate voltage becomes higherthan cell thresh hold voltage depending upon the data stored in saidfirst storage site.
 41. The method of reading storage sites of claim 41,wherein said first positive voltage is a value near a programmedthreshold voltage of said memory cell.
 42. The method of reading storagesites of claim 41, wherein said second positive voltage is less thansaid first positive voltage.
 43. The method of reading storage sites ofclaim 41, wherein connecting said ground potential to said firstdiffusion further comprises: a) selecting a column selector gateconnecting said ground potential to said column, b) applying a positivevoltage to word lines of unselected memory cells between said columnselector and said first diffusion.
 44. The method of reading storagesites of claim 41, wherein connecting said second positive voltage tosaid second diffusion further comprises: a) selecting a column selectorgate connecting said second positive voltage to said column, b) applyinga positive voltage to word lines of unselected memory cells between saidcolumn selector and said second diffusion.
 45. The method of readingstorage sites of claim 41 further comprising: a) said second positivevoltage connected to said second diffusion produces a low thresholdvoltage for said second storage site, b) said first storage site has ahigh threshold voltage when charged with electrons representing saidfirst storage site not being programmed thereby blocking a flow ofcurrent, c) said first storage site has said low threshold voltage whennot charged with electrons representing said first storage site beingprogrammed thereby allowing said flow of current, d) said flow ofcurrent indicates a stored data value in said first storage site.
 46. Asecond method to produce a twin MONOS memory cell array, comprising: a)preparing a semiconductor substrate to form cells of a twin MONOS memoryarray, b) forming mask elements on a surface of said semiconductorsubstrate, c) implanting a lightly doped region between said maskelements and within said lightly doped region implanting a heavily dopedregion, d) forming a first insulator between said mask elements oversaid lightly doped region, e) planarizing the surface of said substrate,and stopping when said mask elements are detected, f) removing said maskelements and forming a second insulator over the surface of saidsubstrate, g) forming a third insulator over the second insulator, g)forming polysilicon sidewall spacers on vertical edges of said thirdinsulator between regions of said first insulator and removing exposedareas of said third insulator and subsequently exposed second insulatorand gate isolation insulator, h) forming a fourth insulator over theexposed surface of the substrate and the sidewall spacers, i) filling afirst void between sidewall spacers and the fourth insulator with apolysilicon fill, j) removing said polysilicon fill to approximately ahalf height from the surface of the substrate, creating a second voidand exposing a portion of the fourth insulator, k) Filling said secondvoid with a metal connecting said polysilicon sidewalls with saidpolysilicon fill.
 47. The method of claim 47, wherein preparing saidsemiconductor substrate further comprising: a) forming shallow trenchisolation in locations between columns of cells of said memory array, b)growing a gate oxide of between about 2-5 nm.
 52. The method of claim 47wherein said semiconductor substrate is a p-type substrate with asurface concentration of between about 5E17 and 1.5E18 atoms per cm³.53. The method of claim 47, wherein forming said mask elements furthercomprises: a) depositing between about 100-250 nm of polysilicon usingCVD, b) depositing on said polysilicon a nitride to a thickness betweenabout 100-150 nm, c) patterning and etching said mask elements.
 54. Themethod of claim 47, wherein implanting said lightly doped region is to aconcentration of between about 3E12 and 3E13 atoms per cm³.
 55. Themethod of claim 51, wherein implanting said lightly doped region is atan energy level of between about 15-20 keV.
 56. The method of claim 47,wherein implanting said heavily doped region further comprises: a)forming said sidewall spacers on said mask elements partially extendingover said lightly doped region, b) implanting said heavily doped regionto a concentration of approximately about 1.5E15 atoms per cm³.
 48. Themethod of claim 53, wherein implanting said heavily doped region is atan energy level of 15-25 keV.
 49. The method of claim 47, whereinforming said first insulator between said mask elements is done bydepositing an oxide using CVD to a thickness of between about 250-400nm.
 50. The method of claim 47, wherein planarizing said surface of thesubstrate uses a chemical and mechanical polish stopping at a nitridelayer of said mask elements.
 51. The method of claim 47, whereinremoving said mask elements further comprises: a) removing an uppernitride layer using a selective etch, b) removing a polysilicon layerusing a selective etch using a dry chemical etch, c) removing a gateisolation oxide formed during said preparation of said substrate, d)growing a new gate oxide using a thermal process to a thickness of 2.5-5nm.
 57. The method of claim 47, wherein forming said third insulatorover the second insulator is to a thickness of in a range ofapproximately 4 nm-7 nm using a CVD process.
 58. The method of claim 47,wherein forming said fourth insulator to a thickness in a rangeapproximately between 2.5 nm and 6 nm.
 59. The method of claim 47,wherein filling said second void with said metal comprises a barriermetal.
 60. The method of claim 60, wherein said barrier metal istitanium nitride.
 61. The method of claim 60, wherein said barrier metalis titanium.